// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
 * Copyright (C) 2020 frank@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN50IW12_H_
#define _DT_BINDINGS_CLK_SUN50IW12_H_

#define	CLK_OSC12M		0
#define	CLK_PLL_CPUX		1
#define	CLK_PLL_DDR0		2
#define	CLK_PLL_PERIPH0		3
#define	CLK_PLL_PERIPH0_2X	4
#define	CLK_PLL_PERIPH1		5
#define	CLK_PLL_PERIPH1_2X	6
#define	CLK_PLL_GPU		7
#define	CLK_PLL_VIDEO0		8
#define	CLK_PLL_VIDEO0_4X	9
#define	CLK_PLL_VIDEO1		10
#define	CLK_PLL_VIDEO1_4X	11
#define	CLK_PLL_VIDEO2		12
#define	CLK_PLL_VIDEO2_4X	13
#define	CLK_PLL_VE		14
#define	CLK_PLL_ADC		15
#define	CLK_PLL_VIDEO3		16
#define	CLK_PLL_VIDEO3_4X	17
#define	CLK_PLL_AUDIO		18
#define	CLK_CPUX		19
#define	CLK_AXI			20
#define	CLK_CPUX_APB		21
#define	CLK_AHB			22
#define	CLK_APB0		23
#define	CLK_APB1		24
#define	CLK_MBUS		25
#define	CLK_MIPS		26
#define	CLK_BUS_MIPS		27
#define	CLK_GPU			28
#define	CLK_BUS_GPU		29
#define	CLK_CE			30
#define	CLK_BUS_CE		31
#define	CLK_VE_CORE		32
#define	CLK_BUS_VE		33
#define	CLK_BUS_AV1		34
#define	CLK_BUS_VE3		35
#define	CLK_BUS_DMA		36
#define	CLK_MSGBOX		37
#define	CLK_SPINLOCK		38
#define	CLK_TIMER0		39
#define	CLK_TIMER1		40
#define	CLK_TIMER2		41
#define	CLK_TIMER3		42
#define	CLK_TIMER4		43
#define	CLK_TIMER5		44
#define	CLK_BUS_TIMER0		45
#define	CLK_BUS_DBG		46
#define	CLK_BUS_PWM		47
#define	CLK_BUS_IOMMU		48
#define	CLK_DRAM		49
#define	CLK_MBUS_DMA		50
#define	CLK_MBUS_VE3		51
#define	CLK_MBUS_CE		52
#define	CLK_MBUS_AV1		53
#define	CLK_MBUS_NAND		54
#define	CLK_BUS_DRAM		55
#define	CLK_NAND0		56
#define	CLK_NAND1		57
#define	CLK_BUS_NAND		58
#define	CLK_MMC0		59
#define	CLK_MMC1		60
#define	CLK_MMC2		61
#define	CLK_BUS_MMC0		62
#define	CLK_BUS_MMC1		63
#define	CLK_BUS_MMC2		64
#define	CLK_BUS_UART0		65
#define	CLK_BUS_UART1		66
#define	CLK_BUS_UART2		67
#define	CLK_BUS_UART3		68
#define	CLK_BUS_I2C0		69
#define	CLK_BUS_I2C1		70
#define	CLK_BUS_I2C2		71
#define	CLK_BUS_I2C3		72
#define	CLK_SPI0		73
#define	CLK_SPI1		74
#define	CLK_BUS_SPI0		75
#define	CLK_BUS_SPI1		76
#define	CLK_EMAC_25M		77
#define	CLK_BUS_EMAC		78
#define	CLK_BUS_GPADC		79
#define	CLK_BUS_THS		80
#define	CLK_I2S0		81
#define	CLK_I2S1		82
#define	CLK_I2S2		83
#define	CLK_BUS_I2S0		84
#define	CLK_BUS_I2S1		85
#define	CLK_BUS_I2S2		86
#define	CLK_SPDIF0_RX		87
#define	CLK_SPDIF0_TX		88
#define	CLK_SPDIF1_RX		89
#define	CLK_SPDIF1_TX		90
#define	CLK_BUS_SPDIF0		91
#define	CLK_BUS_SPDIF1		92
#define	CLK_AUDIO_HUB		93
#define	CLK_AUDIO_CODEC_DAC	94
#define	CLK_AUDIO_CODEC_ADC	95
#define	CLK_BUS_AUDIO_CODEC	96
#define	CLK_USB_OHCI0		97
#define	CLK_USB_OHCI1		98
#define	CLK_USB_OHCI2		99
#define	CLK_BUS_OHCI0		100
#define	CLK_BUS_OHCI1		101
#define	CLK_BUS_OHCI2		102
#define	CLK_BUS_EHCI0		103
#define	CLK_BUS_EHCI1		104
#define	CLK_BUS_EHCI2		105
#define	CLK_BUS_OTG		106
#define	CLK_BUS_LRADC		107
#define	CLK_ADC			108
#define	CLK_DTMB_120M		109
#define	CLK_TVFE_1296M		110
#define	CLK_I2H			111
#define	CLK_CIP_TSX		112
#define	CLK_CIP_MCX		113
#define	CLK_CIP_TSP		114
#define	CLK_TSA_TSP		115
#define	CLK_CIP27		116
#define	CLK_CIP_MTS0		117
#define	CLK_AUDIO_CPU		118
#define	CLK_AUDIO_UMAC		119
#define	CLK_AUDIO_IHB		120
#define	CLK_TSA432		121
#define	CLK_MPG0		122
#define	CLK_MPG1		123
#define	CLK_BUS_DEMOD		124
#define	CLK_TCD3		125
#define	CLK_VINCAP_DMA		126
#define	CLK_BUS_HDMI_AUDIO	127
#define	CLK_BUS_CAP_300M	128
#define	CLK_HDMI_AUDIO		129
#define	CLK_BUS_TVCAP		130
#define	CLK_DEINT		131
#define	CLK_SVP_DTL		132
#define	CLK_AFBD		133
#define	CLK_BUS_DISP		134

#endif /* _DT_BINDINGS_CLK_SUN50IW12_H_ */
